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COURSE PRO FORMA

IMPORTANT:
Contents of this Pro Forma shall not be changed without the Senate’s approval for items indicated with *. Changes
to the other items can be approved at the Academy/Faculty/Institution/Centre level.

Code KEEE2232

Title Digital Design

Pre-requisite KEEE1131

Student Learning Time (SLT) 120 hours

Credit 3

Learning Outcomes 1. Describe different types of MSI’s devices and implement logic
function using PLD, FPLA, PROM, and PAL
2. Analyze the synchronous and asynchronous sequential circuits
3. Apply sequential circuit with programmable logic Devices

Synopsis This course introduce the different types of MSI’s devices, Combina-
tional logic design with PLDS, Sequential logic design principles, syn-
chronous design with state machine, sequential logic design with
PLD and Circuit design using FPGA’s
Assessment 40 % Continuous Assessments
60 % Final Examination

References 1. Fundamentals of Digital Logic with Verilog Design, 3rd Edition,
Brown and Vranesic, McGraw Hill, 2014.
th
2. Digital design: with an introduction to the Verilog HDL, 5 Edition,
Mano and Cilleti, Pearson, 2012.
nd
3. Digital design and computer architecture, 2 Edition, David Harris
and Sarah Harris, Morgan Kaufman, 2013.
Soft Skills Communication Skills (CS1)
Critical Thinking & Problem Solving (CT1, CT2, CT3)
Lifelong learning & Information Management (LL1)

UM-PT01-PK03-BR003(BI)-S04